Start analyzing the technical challenges and risks with a feasibility study. We cooperate closely during this phase to understand not just the IC requirements but also how the ASIC should function inside the application. This will tell us what requirements are really important, and what are the nice-to-haves. As an independent (fabless) design company, we choose the best process technology (plain CMOS, BCD, RF-SOI or SiGe) based solely on your needs plus clear technology roadmaps and budget constraints. The end result is not a prototype, but a detailed technical report with a proposed architecture and clear agreed, specifications of underling IP blocks, along with NRE projections for the entire development. This serves as a 'go/no-go' input depending on the business case. This is the basis of your decision to further invest in this development.

This phase typically takes 2 to 4 months depending on the complexity of your ASIC requirements.

The circuit design officially starts after the feasibility phase has been completed, but typically some concepts circuits design have their roots in the feasibility phase . Using advanced EDA tools and proven methodologies, with our "first-time-right" mentality, we optimize every circuit element for your specific performance, power, and area requirements. Our experienced IC engineers manage trade-offs between functionality, cost, and manufacturability (DFM) while ensuring your ASIC meets all agreed technical specifications.

Throughout development, we work closely with your team, providing regular design reviews and milestone updates. This phase typically takes 12 to 18 months to complete

This phase ends when we send the design, the GDSII file to the foundry for mask making and production. The production itself typically takes 3 to4 months, after which assembly and packaging takes another month.

This is the phase where first prototype devices become available. These prototypes undergo extensive characterization measurements both functional and parametric, to ensure a flawless and reliable operation across all conditions in real-world application. We confirm compliance with your specifications, verify performance margins, and identify potential production yield issues. Especially for RF design, it is crucial to correlate the real-life bench measurements with our simulation results. Simulation models and PDKs are always an abstraction of actual silicon performance. Typically our designs are first time functional right, and will require minor design updates and a new silicon spin though the foundry.
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Once we are satisfied that these prototypes are functional and performing, we release them to you, so you can validate these devices in the intended application. Your application validation results are again compared to our measurement result to ensure we have met all requirements in every aspect.

Qualification has two distinct aspect: Validating your ASIC's performance over its intended production lifetime, and ensuring that the device can be handled during packaging and mounting during assembly into the application. Our comprehensive testing protocol includes every aspect that is relevant for your IC, such as: accelerated aging, temperature cycling, humidity exposure, and electrical stress testing (ESD) to predict long-term behavior and failure rates. With corner lot wafers, normal process variations during production are deliberately induced, exposing potential sensitivities in the design that in influence the performance. With statistical analysis of measurement data from these corner lots devices,  we update the test limits of the production test ensuring each device delivered to you will perform according to the specification over lifetime and production variations, and compliance with relevant industry standards.

This rigorous qualification process provides the documentation and confidence needed for successful product launches, giving you assurance in your ASIC's long-term performance and reliability.