This study will try to tackle one or two of the drawback of the JTAG boundary scan, namely the higher design effort and potentially, a second drawback can be tackled as well, reduce the extra pin count by sharing the JTAG pins with a SPI interface.

This design will consist out of several parts. You are looking into the theory and behavior modelling of charge pumps, compare different architectures and, of course, implement the best one in a certain IC process. If needed only one or two parts will be carried out.

For an ultra linear and broadband RF receiver test chip, developed at bruco, we have difficulties determining the realized noise figure and distortion. The receiver chip outputs 2 quadrature IF signals differentially that should not be loaded when measured. This is a challenge as most sensitive measurement equipment is designed to operate in 50 Ohm single-ended. In this assignment you are going to investigate the different options to tackle this measurement challenge.

In RF IC design, the performance of the design is often significantly depending on the layout parasitics. For finding the capacitance between traces or trace to substrate and also the resistance between connections, it is common to use extraction software that generates a new netlist including the parasitics of interest. For RF design not only the Capacitance and resistance is important, but also the inductance. For this an Electro-Magnetic (EM) simulator is used. Compared to the more standard RC extraction tools, that can handle all design layers and will even recognize active devices, the EM simulator can only be used for the back-end metal stack. In this assignment the preparation of the layout for such an EM simulator, with scripting is investigated.

In stead of trying to design an amplifier that is almost linear enough to process the modern wireless signals and apply DPD techniques to it, you are investigating the possibility to optimize the design to fit easy pre-distortion.

A low dropout (LDO) regulator is one of the most basis building blocks in a electronic design. In this assignment you are going to investigate the possibility to optimize the LDO design w.r.t. load variation and the relation to bias current usage.

After design and fabrication an IC must be evaluated on the bench. In this assignment you are going to investigate how to measure an IC that generates very low harmonic power without increasing the input power, as this will damage the IC.