
Designing high-performance handheld test equipment requires resolving the conflict between wide system bandwidth and strict galvanic isolation safety requirements. This case study details the architecture of the ICON500, a custom Bipolar ASIC developed to drive isolation barriers in the Fluke ScopeMeter® while maintaining a 500 MHz signal path.

The primary engineering challenge for the fourth-generation Fluke ScopeMeter® was maintaining a 500 MHz system bandwidth while supporting fully isolated input channels. Unlike benchtop oscilloscopes with a common ground, a handheld safety tool requires a "Floating Ground" mode.
This architecture introduces a floating interface between the signal conditioner and the acquisition device. The signal path must traverse a galvanic isolation barrier—specifically a combination of an HF-transformer and an optocoupler—which significantly impacts frequency response. The objective was to design a preprocessing ASIC that could drive this isolation barrier without becoming the system bottleneck, ensuring the total signal chain met the 500 MHz requirement.
We developed the ICON500 (Input CONditioner 500MHz BW), an analog ASIC positioned directly behind the input BNC connector. The chip functions as the primary signal conditioner, transforming input signals to levels compatible with the acquisition system.
The ASIC supports two distinct operational modes:
In Floating Ground mode, the system bandwidth relies on the cascade of four critical stages:
While the Common Ground mode offered sufficient margin, the Floating Ground mode presented strict limitations. The external capacitive divider and the HF-transformer required for galvanic isolation were identified as the primary bandwidth bottlenecks.
A standard breakdown of -3 dB bandwidth per component proved insufficient for this design. Because the roll-off slope of the individual stages—particularly the transformer and attenuator—is generally higher than first-order, simple cascading calculations would yield misleading results. We performed exact response modeling for each component to accurately predict and guarantee the 500 MHz system-level performance.
To achieve the required linearity and drive capability at these frequencies, we selected a 350nm Bipolar process. This node provided the necessary breakdown voltages and transistor speed for the analog front-end requirements.


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