Miniaturizing Fiber-Optic Sensing: From Rack-Mount to ASIC-Ready Module

The Engineering Challenge: Precision in a Restricted Envelope

Technobis utilizes an Application Specific Photonic Integrated Circuit (ASPIC) based on Indium Phosphide to measure strain, shape, and temperature via optical fibers. The readout electronics for this ASPIC traditionally required substantial physical space and power.

The objective was aggressive: reduce the form factor from a shoebox/rack size to a handheld device (Gen 3A) and ultimately a single ASIC (Gen 3B) to make the technology viable for disposable medical endoscopes and widespread industrial IoT.

Why FBG Interrogators Matter

The miniaturization of this FBG (Fiber Bragg Grating) interrogator technology opens up critical applications where standard electronic sensors fail due to size, weight, or electromagnetic interference (EMI):

• Medical Interventions: In minimally invasive surgery, fiber optics are used in catheters, endoscopes, and guide wires to sense shape, temperature, and pressure in real-time without X-ray guidance.
• Aerospace: "Structural Health Monitoring" of composite materials in modern aircraft wings and fuselages, where sensors must be lightweight and immune to lightning strikes or EMI.
• Industrial & Energy: Monitoring downhole equipment in oil and gas or high-tech machinery where robust, precise strain measurement is required in harsh environments.

Technical Approach: The "Gen 3A" Intermediate Step

Moving directly from a rack-mounted system to a custom ASIC involves significant risk and lead time. We mitigated this by developing "Gen 3A" first—a highly optimized implementation using discrete components that mimics the future ASIC architecture.

• ASPIC Control: We designed the drive circuitry to precisely control the optical chip's light sources and modulators.
• Signal Chain: The core challenge was the Transimpedance Amplifier (TIA). The optical feedback requires extreme sensitivity; the electronics must amplify nano-ampere currents with minimal noise introduction.
• Data Processing: We integrated a high-speed ADC and an STM32 microcontroller to sample the TIA output and process the data locally, utilizing an RS-485 interface for robust device control and firmware updates.

Roadmap to ASIC (Gen 3B)

The current module achieves a 5x reduction in Bill of Materials (BOM) cost. The next phase, currently in architecture planning, integrates the TIA, ADC, and driver stages into a custom Mixed-Signal ASIC. This integration is projected to reduce the BOM by a factor of 50 compared to the original system, unlocking high-volume markets.

Results

• Speed: From concept to working prototype in just four months.
• Form Factor: Successfully reduced to a memory-stick size dimensions.
• Scalability: Validated the electrical architecture needed for the final ASIC integration.

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